Title: Energy-efficient circuit technologies for sub-14nm microprocessors and SoCs: challenges and opportunities
This seminar presents some of the prominent barriers to designing energy-efficient circuits in the sub-14nm technology regime and outlines new paradigm shifts necessary in next-generation multi-core microprocessors and systems-on-chip. Emerging trends and key challenges in sub-14nm design are outlined, including (i) device and on-chip interconnect technology projections, (ii) performance, leakage and voltage scalability, (iii) special-purpose hardware accelerators and reconfigurable co-processors for compute-intensive signal processing algorithms, (iv) fine-grain power management with integrated voltage regulators, and (v) resilient circuit design to enable robust variation-tolerant operation. Attendance is free!
Lecturer: Ram Krishnamurthy, Intel Corporation
Date: Wed, July 13, 2016 @ 21:00 – 23:00 (Bucharest local time)
Registration link: Click here!