IEEE Region 6 Central Area
- This event has passed.
CASS Distinguished Lecturer Event “Dissecting Design Choices in Continuous-time Delta-Sigma Converters” Dr. Shanti Pavan, IIT Madras
September 26, 2019 @ 9:00 pm - 11:00 pm
Co-sponsored by: Solid State Circuits Society (SSCS), Signal Processing Society
CASS Distinguished Lecturer Event with Dr. Shanti Pavan:
“Dissecting Design Choices in Continuous-time Delta-Sigma Converters”
Event sponsored and organized by:
Circuits and Systems Society – Santa Clara Valley Chapter (CASS-SCV)
Co-sponsors:
DATE & TIME:
Thursday, September 26th, 2019. 6 PM – 8 PM
PROGRAM:
6:00 – 6:30 PM Check-in / Networking & Refreshments
6:30 – 7:30 PM Lecture
7:30 – 7:45 PM Q&A
7:45 PM Adjourn
LOCATION:
UCSC Silicon Valley Extension
3290 Scott Blvd, Santa Clara, CA 95054
AGENDA:
TITLE: Dissecting Design Choices in Continuous-time Delta-Sigma Converters
ABSTRACT:
Continuous-time Delta-Sigma Modulators (CTDSMs) are a compelling choice for the design of high resolution analog-to-digital converters. Many delta-sigma architectures have been published (and continue to be invented). This leaves the designer with a bewildering array of choices, many of which seem to pull in opposite directions. Further, it is often difficult to make a clear comparison of various architectures, as they have been designed for dissimilar specifications, by different design groups, and in different technology nodes. This talk examines various alternatives for the design of power efficient single-loop continuous-time delta sigma converters.
BIO:
Shanthi Pavan received the B.Tech from IIT Madras in 1995 and the doctoral degree from Columbia University, New York City, in 1999. He is currently a Professor of Electrical Engineering at IIT Madras. His research interests are in the areas of high speed analog circuit design and signal processing.
He is a recipient of many awards, including the IEEE Circuits and Systems Society Darlington Best Paper Award (2009) , the Swarna Jayanthi Fellowship (2009) and the Shanti Swarup Bhatnagar Award (2012). He has served as the Editor-in-Chief of the IEEE Transactions on CIrcuits and Systems:Regular Papers. He has served on the Technical Program Committee at the International Solid State Circuits Conference (ISSCC), and as a Distinguished Lecturer of the Solid-State Circuits Society. He is currently a distinguished lecturer of the IEEE Circuits and Systems Society. He is a fellow of the Indian National Academy of Engineering (INAE) and the Institute of Electrical and Electronic Engineers (IEEE). He is the coauthor (with Richard Schreier and Gabor Temes) of “Understanding Delta Sigma Converters”, published by the Wiley-IEEE Press.
Speaker(s): Shanti Pavan,
Agenda:
CASS Distinguished Lecturer Event with Dr. Shanti Pavan:
“Dissecting Design Choices in Continuous-time Delta-Sigma Converters”
Event sponsored and organized by:
Circuits and Systems Society – Santa Clara Valley Chapter (CASS-SCV)
Co-sponsors:
DATE & TIME:
Thursday, September 26th, 2019. 6 PM – 8 PM
PROGRAM:
6:00 – 6:30 PM Check-in / Networking & Refreshments
6:30 – 7:30 PM Lecture
7:30 – 7:45 PM Q&A
7:45 PM Adjourn
LOCATION:
UCSC Silicon Valley Extension
3290 Scott Blvd, Santa Clara, CA 95054
AGENDA:
TITLE: Dissecting Design Choices in Continuous-time Delta-Sigma Converters
ABSTRACT:
Continuous-time Delta-Sigma Modulators (CTDSMs) are a compelling choice for the design of high resolution analog-to-digital converters. Many delta-sigma architectures have been published (and continue to be invented). This leaves the designer with a bewildering array of choices, many of which seem to pull in opposite directions. Further, it is often difficult to make a clear comparison of various architectures, as they have been designed for dissimilar specifications, by different design groups, and in different technology nodes. This talk examines various alternatives for the design of power efficient single-loop continuous-time delta sigma converters.
BIO:
Shanthi Pavan received the B.Tech from IIT Madras in 1995 and the doctoral degree from Columbia University, New York City, in 1999. He is currently a Professor of Electrical Engineering at IIT Madras. His research interests are in the areas of high speed analog circuit design and signal processing.
He is a recipient of many awards, including the IEEE Circuits and Systems Society Darlington Best Paper Award (2009) , the Swarna Jayanthi Fellowship (2009) and the Shanti Swarup Bhatnagar Award (2012). He has served as the Editor-in-Chief of the IEEE Transactions on CIrcuits and Systems:Regular Papers. He has served on the Technical Program Committee at the International Solid State Circuits Conference (ISSCC), and as a Distinguished Lecturer of the Solid-State Circuits Society. He is currently a distinguished lecturer of the IEEE Circuits and Systems Society. He is a fellow of the Indian National Academy of Engineering (INAE) and the Institute of Electrical and Electronic Engineers (IEEE). He is the coauthor (with Richard Schreier and Gabor Temes) of “Understanding Delta Sigma Converters”, published by the Wiley-IEEE Press
Location:
UCSC Silicon Valley Extension
3290 Scott Blvd
Santa Clara, California
95054