IEEE
September 9th, 2013

IEEE Components, Packaging and Manufacturing Technology Society – OC Chapter

Integrated Circuit ESD/Latch-up Mechanisms and Testing

Barry Fernelius, Manager at Evans Analytical Group (EAG)

 Orange County, CA

 

Abstract

Design engineers are increasingly being challenged to reduce the incidence of latch-up. At the same time, this task is made more difficult as devices become more complex and process technologies continue to shrink. The JEDEC latch-up spec is also constantly evolving. In this presentation, attendees will learn:

  • An overview of latch-up test and spec
  • Test guidelines, techniques, and best practices
  • Why latch-up is challenging
  • What’s coming in JESD78E

Biography

Mr. Barry Fernelius is the manager of the ESD and latch-up labs at Evans Analytical Group. He has been working in the semiconductor industry since 1981, and he’s been involved with the JEDEC ESD and latch-up specs for more than twenty years. He’s also been a fab engineer for Hewlett-Packard and a senior reliability engineer for Agilent and Avago.

Barry Fernelius


 Date: Thursday, September 12, 2013

Location: Broadcom Corporation, 5300 California Ave., Irvine, CA 92617 – Bldg. 2 Conf. Room 2-1034

Check in at the Security Gate and proceed to Bldg. 2. You will be escorted into the building.

Time: 5:30-6:00pm: Social time, 6:00-7:00pm: Presentation, 7:00pm: Dinner (free for attendees!)

RSVP: IEEE members and non-members all are welcome to attend.

Please RSVP at http://tinyurl.com/ohang2c. Please be at the Bldg. 2 entrance by 6:00 pm.

For questions regarding RSVP, please contact Cristina Nicoara (cnicoara@broadcom.com).

August 15th, 2013

IEEE Components, Packaging and Manufacturing Technology Society – OC Chapter

Wafer Bonding Enables New Technologies and Applications for 3D-IC 

Mark Franklin, Vice President and Chief Technology Officer

Teikoku Taping Systems – TTS America

 

Abstract

3D packaging saves considerable space and increases device speeds by stacking the devices in a single package for power reduction and performance improvement. Whether this bonding process for the stacked chips are activated by temperature, plasma, or chemicals, the technology of wafer bonding is unifying different materials to create new devices and micro components that cannot be fabricated using silicon alone. Wafer bonding is fueling silicon-on-insulator (SOI), MEMS, MOEMS, and 3D-IC packaging. 

 

Biography

Mr. Mark Franklin joined Teikoku Taping Systems in 2011 as Vice President and Chief Technologist responsible for advanced technical roadmap development. Mr. Franklin received his B.S.E.E. from Templeton University and holds eight patents in plasma etch, MEMS processing methods and wafer bonding. Mr. Franklin has served in engineering positions at Texas Instruments machine science and Technology Center, LSI Logics Top secret government contract facility, Silicon Genesis where lead a team that designed the surface activation source now used by EV Group and at Suss MicroTec.

Mark Franklin 


 

Date: Thursday, August 29, 2013

Location: Broadcom Corporation, 5300 California Ave., Irvine, CA 92617 – Bldg. 2 Conf. Room 2-1037

Check in at the Security Gate and proceed to Bldg. 2. You will be escorted into the building.

Time: 5:30-6:00pm: Social time, 6:00-7:00pm: Presentation, 7:00pm: Dinner (free for attendees!)

RSVP: IEEE members and non-members all are welcome to attend.

Please RSVP at http://tinyurl.com/nupuou6. Please be at the Bldg. 2 entrance by 6:00 pm.

For questions regarding RSVP, please contact Cristina Nicoara (cnicoara@broadcom.com).

June 26th, 2013

IEEE Components, Packaging and Manufacturing Technology Society – OC Chapter

SIGNAL INTEGRITY FUNDAMENTALS ONE DAY SHORT COURSE

Instructors:  Stephen Hall & Howard Heck

Intel Corporation

OVERVIEW:  This one-day short course provides practicing design engineers an in-depth introduction into the fundamentals of signal integrity. It covers the practical and theoretical aspects necessary to design modern high-speed digital systems at the chip, package, and board levels. Attendees will learn from Stephen Hall and Howard Heck, two leading experts from Intel Corporation.

WHO SHOULD ATTEND:  Engineers and engineering managers who need a detailed introduction to signal integrity, layout engineers who support high-speed design, and serial I/O buffer circuit designers.

TOPICS:

  • High Frequency SI Challenges
  • Transmission lines
  • Skin effect, dielectric loss, and surface roughness
  • Single-ended and differential signaling
  • Cross-talk
  • Eye diagram analysis
  • High-speed serial interconnections
  • Equalization and de-emphasis
  • Jitter
  • Simultaneous Switching Output noise (SSO)
  • Power distribution

ABOUT THE INSTRUCTORS:

Stephen Hall:   Stephen began his career in 1992 in the Special Purpose Processor Division of the Mayo Foundation developing multi-gigabit modeling for X-band digital radar and serial optical links. In 1996, he joined Intel, as lead designer for buses on Pentium® II, III and IV, coordinated research with universities, led research teams in high-speed modeling and taught Signal Integrity courses. He published the textbook “High-Speed Digital System Design” in 2000 and co-authored “Advanced Signal Integrity for High-Speed Digital Designs” in 2009 with John Wiley & Sons. From 2003 to 2007, he researched new modeling and measurement for channel speeds up to 30 Gb/s and is currently investigating signal integrity associated with high performance small form factor computing devices. Stephen holds 25 patents (issued and pending) and has authored/co-authored 26 journal and conference papers.

Howard Heck:  Since joining Intel in 1995, Howard held R&D engineering and management positions for system electrical technologies (interconnect, power, EMI). He led development for Pentium® II 100 MHz Host Bus, earning an Intel Achievement Award, and managed teams that defined and delivered technology for Direct RDRAM™ DDR II, Pentium® 4 Host Bus, and Accelerated Graphics Port (AGP) interfaces. Prior to DEG, he led Advanced Signaling Technologies in Intel’s Systems Technology Lab, focusing on modeling, simulation, measurement, and technology for 10+ Gb/s signaling. He currently leads specifications and interconnect solutions for USB 3.0 technology. Howard earned the B.S.Ch.E. degree from Northwestern University in 1985, and the M.S.E.E. degree from the National Technological University in 1994. From 1985-1995 he was employed by IBM’s PCB manufacturing and high performance packaging lab, where he led electrical development of HyperBGA™packaging technology. Since 1997, Howard has served as Adjunct Professor at Oregon Graduate Institute, where he teaches High Speed Digital Interconnect Design. He has presented papers at several industry conferences, holds ten patents with twelve pending and is a Senior Member of the IEEE.  

AGENDA:

Tentative Agenda_SI course

 


 Date:              Friday, July 19th

Location:      Calit2 Building, University of California – Irvine    (please see map below)

Parking will be available in the Advanced Parking Structure (APS) off East Peltason Drive.

Time:              7:45am – 5:10pm

RSVP:            IEEE members – $30; Non-members of IEEE – $40; Students – $30  

Prices will increase by $10 for non-student registrations on July 1, 2013

                     Please RSVP at  http://www.eventbrite.com/event/5563921840#.

For questions regarding RSVP, please contact Raj Peddi  (Raj.Peddi@us.henkel.com).

UCI parking map

 

June 12th, 2013

IEEE Components, Packaging and Manufacturing Technology Society – OC Chapter

The Latest Technology Trend of Packaging Materials for Power Devices

Ken Uchida, Director of Technology and Development Division

KYOCERA CHEMICAL Corporation, Japan

Abstract

In today’s mobile devices market, the demand for higher powered consumer products is increasing.  As a response to this increase in demand, the importance of thermal management is reaching critical mass.  One method of addressing thermal management is found in the encapsulating material for power devices.  The encapsulating material would require high heat dissipation and high thermal conductivity.  Thermal management is especially important in the application of cutting edge power devices, such as the SiC device, where the junction temperature range has no limitation.  In order to push the performance envelope on new devices, enhancement in heat resistance of the surrounding material is highly critical.  Suitable constitution of appropriate encapsulation material and its ensuing effects on device reliability will be introduced at this technical meeting.  

Biography

After earning a Master’s degree in energy material from the Yokohama National University in 1984, he joined the research and development center at Toshiba and was involved in the development of organic material for semiconductor devices.  In 1994, he transferred to Toshiba Chemical Corporation. In 2002, the company changed its name to Kyocera Chemical Corporation.  At Kyocera Chemical Corporation, Mr. Uchida has been engaged in the development of encapsulation resin used in semiconductor devices.

Ken Uchida picture

 


 

Date:              Tuesday, June 25, 2013

Location:       Broadcom Corporation, 5300 California Ave., Irvine, CA 92617 – Bldg. 2 Conf. Room 2-1037 

Check in at the Security Gate and proceed to Bldg. 2. You will be escorted into the building.

Time:              5:30-6:00pm: Social time, 6:00-7:00pm: Presentation, 7:00pm: Dinner (free for attendees!)

RSVP:            IEEE members and non-members all are welcome to attend.

                     Please RSVP at http://tinyurl.com/nth44jx.  Please be at the Bldg. 2 entrance by 6:00 pm.

For questions regarding RSVP, please contact Cristina Nicoara (cnicoara@broadcom.com).

May 24th, 2013

IEEE Components, Packaging and Manufacturing Technology Society – OC Chapter

Recent Advances in Anisotropic Conductive Films (ACFs) Technology

Dr. Kyung W. Paik, Professor in the Department of Materials Science and Engineering

Korea Advanced Institute of Science and Technology (KAIST)

Abstract

Anisotropic Conductive Films (ACFs) have been widely used as interconnection materials in semiconductor and display applications for chip-on-glass (COG), flex-on-glass (FOG), flex-on-board (FOB), chip-on-flex (COF), chip-on-board (COB) due to their fine-pitch capability, simple process, and cost effectiveness. There have been many technical innovations in terms of materials and processing technologies. In this presentation, solder ACFs, nanofiber, photo-activated ACFs and 3D-TSV NCF materials will be presented as recent ACF materials innovation, and novel vertical ultrasonic bonding technique and wafer level ACF processing methods will be presented as recent ACF processing innovation.

For nanofiber ACFs, about 500 nm diameter polymer nanofibers with coupled conductive particles are fabricated using an electro-spinning method, and then ACFs with the nanofibers are successfully made by laminating NCFs (nonconductive films) on top and bottom side of the nanofibers. This novel ACF shows excellent electrical bump contact resistance and fine pitch handling capability. Nanofiber ACF can completely solve the electrical shortage problems at 7 μm bump-to-bump gap and 20 micron ultra fine bump pitch of COG(Chip On Glass) and COF(Chip On Flex) electronic packaging applications.

Wafer level packages using pre-applied ACFs are also invented. After ACF pre-lamination on a bumped wafer, singulated chips are assembled on substrates using thermo-compression bonding. Wafer level assembled ACF joints showed excellent contact resistance, strong bump adhesion, and similar reliability behaviors compared with conventional ACF flip chip joints using thermo-compression bonding. The new wafer level packages using pre-applied ACFs can be used in many non-solder flip chip assembly applications such as COB (Chip-on-Board), COF (Chip-on-Flex), COG (Chip-on-Glass), and 3D-TSV. The non-conductive films (NCFs) or TSV NCFs, are applied on the wafer level before bonding so that it acts as both adhesive and underfill. Excellent SnAg bump joints were successfully formed with stable electrical interconnection by the added flux function at 40 um pitch 3D-TSV bump pitch.

Biography

After receiving his Ph.D. from Cornell University in 1989, Dr. Kyung W. Paik worked for General Electric from 1989 to 1995, where he was involved with R&D of materials and processes of GE High Density Interconnect (HDI) multichip module technology and power I/C packaging.  In 1995, he joined the Korea Advanced Institute of Science and Technology (KAIST) as a professor in the Materials Science and Engineering Department, serving as VP of Research from 2011 to 2013.  In his Nano-Packaging and Interconnect Laboratory (NPIL), he currently works on Anisotropic Conductive Adhesives (ACAs) materials and processing, 3-D TSV interconnect materials, solders, and MEMS & display packaging technologies. Professor Paik has published more than 150 SCI journal papers and has about 40 issued and pending US patents.  He is a member of IEEE-CPMT, IMAPS, and SEMI and has been involved in numerous international electronic packaging conferences such as ECTC, IMPACT, EMAP, and EPTC, from invited speaker and international liaison, to organizer, chair, and technical committee member.

 June Tech Speaker_Professor Paik


 

Date:              Tuesday, June 4, 2013

Location:       Broadcom Corporation, 5300 California Ave., Irvine, CA 92617 – Bldg. 2 Conf. Room 2-1037 

Check in at the Security Gate and proceed to Bldg. 2. You will be escorted into the building.

Time:              5:30-6:00pm: Social time, 6:00-7:00pm: Presentation, 7:00pm: Dinner (free for attendees!)

RSVP:            IEEE members and non-members all are welcome to attend.

                     Please RSVP at http://tinyurl.com/oueh59t.  Please be at the Bldg. 2 entrance by 6:00 pm.

For questions regarding RSVP, please contact Cristina Nicoara (cnicoara@broadcom.com).

April 18th, 2013

IEEE Components, Packaging and Manufacturing Technology Society – OC Chapter

DRAM Market Forces of Fragmentation & Consolidation

Bill Gervasi, Computer Memory Technology Analyst, Discobolus Designs

Abstract

The market for DRAMs (Dynamic Random-Access Memory) has been a dominant force in computer architecture choices, and a healthy friction always exists between the compromises made for mass adoption and the needs of specific applications.  One mainstream architecture thread – Fast Page through SDRAM through DDR – has dominated the scene but there have been a number of interesting successes and failures to fray from that thread, and many more are on the horizon.  Sometimes it’s amazing what tricks people play to squeeze performance from a technology.  Throughout these transitions and experiments one truism never changes: the tradeoff of volume and price drives success.

Biography

Bill Gervasi has been involved in the definition of Double Data Rate SDRAM since its earliest inception.  His background is in computer sciences and career highlights include 19 years at Intel where over the years he was systems hardware designer, software designer, and major accounts manager.  Bill Gervasi joined Intel in 1976 in the computer systems group manufacturing department, eventually leaving Intel in 1995. During that period, the computer industry changed from computers that filled rooms the size of basketball courts to desktop and laptop form factors in nearly every home in the world.

 Since then, Mr. Gervasi specialized in the computer memory technology arena, getting involved in international standards and battles for global dominance for this key part of computer systems. He subsequently was with S3 where he was a graphics architecture specialist and at Transmeta as memory technology analyst.  Most recently he has entered the memory modules world through management positions at Netlist, SimpleTech, and US Modular driving unique memory module configurations. 

Mr. Gervasi is credited with successfully introducing 4 rank and DDR3 registered DIMMs into the JEDEC standardization process. He has served on the JEDEC Board of Directors and chaired committees for DRAM parametrics and small form factor memory modules throughout the development of DDR1, DDR2, and DDR3.  As a chairman of the JEDEC standards organization, he has had a role in paving the memory industry roadmap, and contributed to spreading these standards to the world including engagement with foreign governments. Bill is a public speaker in this niche, generating both excitement and controversy with his aggressive vision for change and progress. Mr. Gervasi holds numerous patents in memory and packaging design, and has performed expert witness testimony in major patent cases.

Bill Gervasi speaks often at technology trade events and offers training for memory technology.  He offers computer memory design, marketing, and analysis services through his company, “Discobolus Designs,” and is the author of Nerd Story a humorous personal history of the computer revolution, available online (ISBN 978-1-4524-4622-6). Find out more at http://www.discobolusdesigns.com

 April Tech Speaker_Bill Gervasi_2


 

Date:              Tuesday, April 30, 2013

Location:       Broadcom Corporation, 5300 California Ave., Irvine, CA 92617 – Bldg. 2 Conf. Room 2-1037 

                        Check in at the Security Gate and proceed to Bldg. 2. You will be escorted into the building.

 Time:              5:00-5:30pm: Social time, 5:30-7:00pm: Presentation, 7:00pm: Dinner

 RSVP:            IEEE members and non-members all are welcome to attend.

                     Please RSVP at http://tinyurl.com/cvl8ez7. Please be at the Bldg. 2 entrance by 5:30 pm.

                          For questions regarding RSVP, please contact Cristina Nicoara (cnicoara@broadcom.com).

August 3rd, 2012

IEEE CPMT Orange County Chapter will hold August technical meeting as follows:

Topic:     Atomic Layer Deposition/Molecular Layer Deposition for Packaging 

Speaker:    Dr. Y. C. Lee, S.J. Archuleta Professor, Director of DARPA Center for Integrated Micro/Nano-Electromechanical Transducers (iMINT), Administrative Director of Nano Materials Characterization Facility (NCF)

Date:   Thursday, August 16, 2012

Time:   6 – 7pm, dinner (pizza and soda provided by CPMT OC Chapter) will be served at the end of the presentation

Venue: Broadcom Corporation, 5300 California Ave., Irvine, CA 92617 – Bldg. 2 Conf. Room 2-1037 (Salt Creek)

For more details and RSVP, please visit   https://meetings.vtools.ieee.org/meeting_view/list_meeting/13547.

The Executive Committee of the Chapter invites everyone of you to attend this meeting and actively participate in all our future activities. Also, please feel free to forward this announcement document to all your friends who may be interested in this talk, as this meeting is OPEN to ALL to attend.

You can follow the Chapter activities on our website at http://site.ieee.org/ocs-cpmt or on LinkedIn at http://www.linkedin.com/groups?gid=3996387&trak=hb_side_g.

 

Thanks much for your participation and support.

Best Regards,

Mehdi Saeidi

Co-chair, IEEE CPMT Orange County Chapter Technical Program

E-mail: saeidi@ieee.org

(949) 296-5618

August 2nd, 2012

You are invited to the IEEE, CPMT, and Intertek tutorial on:“Fundamentals of Signal Integrity, Power Integrity and EMI/EMC for Microelectronic Packaging and System Design.” Date: August 23, 2012

Location: Lake Forest, CA

Schedule:
8:30 am – 8:50 am Registration and Networking
9:00 am – 5:00 pm (to include a one hour lunch break and one hour lab tour and demo)

Description:
This course will teach the fundamentals of IC package electrical performance metrics such as signal integrity, power integrity and electromagnetic compatibility and how to apply those concepts to an advanced IC package design. This often complex content will be delivered at a level that should be accessible to the “lay-engineer”.

Flyer:    IEEE_CPMT_OC_Chapter_Aug_23_2012_Sam_Karikalan_David_OReilly

Topics will Include:

  • The basic principles of interconnect electromagnetics, including RLC parasitics, transmission line behavior, and associated common design challenges such as signal reflections, crosstalk, simultaneous switching noise and power delivery network resonances.
  • The relationship between common signal integrity and power integrity design issues and system level electromagnetic compatibility.
  • Other component level causes for inter-system and intra-system EMC issues.
  • Areas of electrical performance concern in typical wafer level, flip chip and wire bonded packages on laminate / build-up substrates (generic electrical design guidelines will be provided).
  • System-level EMC, with various practical EMI mitigation techniques.

Lab Tour: The event will include a visit to Intertek’s state-of-the-art EMC/EMC compliance test labs for a demonstration of common EMI/EMC phenomena.

Presenter:  Sam Karikalan, Senior Principal Engineer, Broadcom Corporation  AND  David O’Reilly, Engineering TEam Leader, Intertek

 

Ticket Type                         Cost
IEEE Member                       $250.00
Non IEEE Member                $400.00
Student IEEE Member           $75.00
Student Non IEEE Member    $125.00

For more information, please contact Kimberly Hawkins at kimberly.hawkins@intertek.com or Sam Karikalan at samk@broadcom.com.

July 31st, 2012

Greetings!

The Program Agenda for the 2012 IEEE-CPMT/IMAPS Advanced Technology Workshop on Optoelectronic Packaging & Assembly has now been published.

http://www.cpmt.org/opto2012/docs/IEEE_CPMT_IMAPS_2012_Opto_ATW_Adv_Announcement_July2012.pdf

This workshop is being held:  September 6 & 7, 2012.    

Location is:  Embassy Suites, 3100 East Frontera Street, Anaheim, CA 92806.

If you are planning to attend, please register early at http://www.eventbrite.com/event/2573756174 and make use of the reduced registration fees. Options available to attend one or both days of the workshop. Students are offered very special rates to benefit from this advanced technology workshop.

The Organizing Committee of the workshop sincerely thanks our Platinum Sponsor, Ansys, and Silver Sponsors, CoSemi, Technic and TopLine for their support to this important event in our region.

 

June 20th, 2012

Dinner Meeting of CPMT OC Chapter on June 27, 2012

The next IEEE CPMT OC Chapter Technical meeting will be held as follows:

Date: Wednesday, June 27, 2012
Time: 5:30pm – 7:00pm
Venue: Broadcom Irvine Campus – Conf. Room 2 -1037
Guest Speaker: Ms. Deborah Patterson, Amkor Technology
Topic: Cu Pillar Flip Chip Usage and Trends

Admission is free to all. Please RSVP at https://meetings.vtools.ieee.org/meeting_view/list_meeting/13039

Hope to see you there!