Archive for the ‘Uncategorized’ Category

IEEE Components, Packaging and Manufacturing Technology Society – OC Chapter

Thursday, Sept 17, 2015 Technical Meeting

Apple Watch Teardown and Others

Bill Cardoso, PhD

Creative Electron

Abstract

Teardowns are powerful tools to gain invaluable insight on how things are designed and built. Critical lessons can be learnt from this process to improve our jobs as designers and manufacturers of electronic products. The Apple Watch went from novelty to market leader in just a few weeks. Added to its impressive commercial success, this device is an incredible work of electronic packaging design. In this presentation we will show the details of the Apple Watch teardown, showing its many layers and complexities. We augment the teardown with x-ray images of several parts of the Apple Watch to gain extra insights on how this tightly packaged device is assembled. We will also present other similar teardowns, including cell phones and wearables.

Biography

Bill started his first company in Brazil at age 17 and sold it a few years later when invited by the US Department of Energy to work at Fermi National Accelerator Laboratory to do nuclear and high energy physics research. As the Department Head for Systems Engineering and after a 10-year long career at Fermilab, Bill moved from Chicago to sunny California to start Creative Electron. True to the American Dream, Creative Electron quickly grew from Bill’s garage to the largest US manufacturer of x-ray machines for the electronics industry (no longer in his garage). At Creative Electron Bill leads the team of engineers who designs and manufactures x-ray systems that are shipped worldwide. Starting with an associate degree at age 13, Bill has a BS, MS, and PhD degrees in Electrical and Computer Engineering and an MBA from The University of Chicago. Bill is the president of the SMTA San Diego chapter and member of the technical committee for SMTA International, SMTA Counterfeit Conference, and SMTA LED Conference, Components for Military and Space Electronics Conference, SPIE Photonics, and the IEEE Nuclear Science Symposium. He is an IEEE Senior member and the author of over 120 technical publications, a contributor to 2 books, owner of a few patents, and a frequent speaker at technical conferences.

Date:              Thursday, September 17, 2015

Location:      Broadcom Corporation, 5300 California Ave., Irvine, CA 92617 – Trestles in Bldg. 2 First Floor

Check in at the Security Gate and proceed to Bldg. 2. You will be escorted into the building.

Time:              5:30-6:00pm: Social time, 6:00-7:00pm: Presentation, 7:00pm: Dinner (free for attendees!)               

RSVP:      IEEE members and non-members all are welcome. Please RSVP at http://tinyurl.com/nmvokh8

Please be at the Bldg. 2 entrance by 6:00 pm; no escorts after that. For questions regarding RSVP, please contact Zijie Cai (zijiecai@broadcom.com).

For more information please contact the following officers of the IEEE CPMT OC Chapter:

Wei Koh: (714) 417-9979                      Alexander Pfeiffenberger: (949) 926-3858                    Jiawei Zhang: (949) 926-3897

*To learn more about the IEEE CPMT OC Chapter, visit us at http://site.ieee.org/ocs-cpmt/ or join us on LinkedIn!*

IEEE Components, Packaging and Manufacturing Technology Society – OC Chapter

Thursday, May 21, 2015 Technical Meeting

Recent Advances in Anisotropic Conductive Films (ACFs) Technology for Wearable Electronics

Kyung W.Paik

Department of Materials Science and Engineering

Nano-Packaging & Interconnect Laboratory

Korea Advanced Institute of Science and Technology(KAIST)

kwpaik@kaist.ac.kr

Abstract

Due to the increasing demand for higher performance, greater flexibility, smaller size, and lighter weight in mobile electronic products, there have been growing needs of wearable electronic products in near future. Wearable watches, glasses, wrist bands, shoes, and clothes have been recently introduced in the market. To realize wearable electronic products, there should be four core electronic hardware technologies – (1) flexible semiconductor, (2)flexible display, (3)flexible battery and (4)flexible packaging & interconnection technologies. In the flexible semiconductor devices, ICs are thinned down to several hundred nanometer thickness, and then transferred to a polymer film. However, much more development is still needed for the real applications of flexible semiconductors in the future. In contrast, flexible displays are already available by introducing OLED (organic LED) realized on polymer films. And flexible batteries are also demonstrated by several companies by adapting solid electrolytes. However, there has been little development on flexible packaging & interconnection areas. As a one of the promising flexible packaging and interconnection technologies, flexible printed circuits (FPCs) substrates and ACF materials based packaging and interconnection will provide the solution for realizing wearable electronic products. In the electronic packaging technology for wearable electronics, flexible IC packaging such as COF(Chip On Flex)/CIF(Chip In Flex) & FOF(Flex On Flex) technologies using FPCs substrates and ACFs materials become very important, because ACF interconnection provides excellent electrical flexibility compared with conventional solder- or socket-based interconnection methods which have a limitation of bending and flexing. In this presentation, it will be presented how the ACFs technology can be successfully used for the COF/CIF and FOF electronic packaging and interconnection methods for wearable electronics applications.

Biography

Kyung W. Paik received the Ph.D. degree from the Cornell University at the department of Materials Science and Engineering in 1989.After the Ph.D. degree, he worked at the General Electric Corporate Research and Development from 1989 to 1995, where he was involved with the R & D of materials and processes of GE High Density Interconnect (HDI) multichip module technology and power I/C packaging as a Senior Technical Staff.  And then, he joined the Korea Advanced Institute of Science and Technology (KAIST) as a professor at the department of Materials Science and Engineering in 1995, and served as the Dean of Student Affairs during 2008 ~ 2000 and the VP of Research during 2011 ~ 2013.  In his Nano-Packaging and Interconnect Laboratory (NPIL), he has been working in the areas of Anisotropic Conductive Adhesives(ACAs) materials and processing, 3-D TSV interconnect materials, solders, and MEMS & display packaging technologies, and has published more than 160 SCI journal papers and has more than 40 issued and pending US patents.  Dr. Paik has been members of the IEEE-CPMT, IMAPS, and SEMI.  And he also has actively involved in numerous international electronic packaging conferences such as ECTC, IMPACT, EMAP, EPTC, and so on as an organizer, technical committee, international liaison, session chairs and invited speakers.

Date:              Thursday, May, 21, 2015

Location:       Broadcom Corporation, 5300 California Ave., Irvine, CA 92617 – Salt Creek

Check in at the Security Gate and proceed to Bldg. 2. You will be escorted into the building.

Time:              5:30-6:00pm: Social time, 6:00-7:00pm: Presentation, 7:00pm: Dinner (free for attendees!)               

RSVP:      IEEE members and non-members all are welcome. Please RSVP athttp://tinyurl.com/mpn8jfu

Please be at the Bldg. 2 entrance by 6:00 pm; no escorts after that. For questions regarding RSVP, please contact Zijie Cai (zijiecai@broadcom.com).

For more information please contact the following officers of the IEEE CPMT OC Chapter:

Wei Koh: (714) 417-9979                      Alexander Pfeiffenberger: (949) 926-3858                    Jiawei Zhang: (949) 926-3897

*To learn more about the IEEE CPMT OC Chapter, visit us at http://site.ieee.org/ocs-cpmt/ or join us on LinkedIn!*

IEEE Components, Packaging and Manufacturing Technology Society – OC Chapter

Copper Pillar VS. Solder Bump: Which is More Reliable?

Craig Hillman, PhD

CEO and managing partner of DfR Solutions

Abstract

With the need for decreasing pitch and higher current densities, copper pillar has surged to the front in regards to the preferred interconnect methodology for flip chip architectures. However, while there are substantial benefits to copper pillar, there can be some misunderstandings as to the risks of copper pillar, especially under certain manufacturing conditions and field environments. In this presentation, Dr. Hillman will present the current state of copper pillar, review the variations in copper pillar offered by the marketplace, and discuss the current knowledge in regards to copper pillar reliability.

Biography

IEEE Components, Packaging and Manufacturing Technology (CPMT) Society Orange County Chapter and UC Irvine Calit2

INTERNET OF THINGS: TECHNOLOGIES ENABLING THE REVOLUTION

Friday, December 5, 2014

UC Irvine Calit2 Auditorium

INTRODUCTION

This one-day workshop provides design engineers an in-depth overview of the design challenges in the Internet of Things. It covers the technical aspects of IoT applications, end-use device design and packaging, semiconductor and sensor devices, wireless connectivity, back-office infrastructure system design, reliability requirements and industry standards. Attendees will learn from leading companies and technical experts in the field.

WHO SHOULD ATTEND:
Engineers and managers who are interested in understanding design challenges for Internet of Things devices and systems.
SPEAKERS:

Matthew Cheng, Broadcom                               M2M Landscape

Dipesh Patel, ARM                                                 ARM Strategy for IoT

Mudasir Ahmed, Cisco                                          Designing for the Internet of Things: A Paradigm Shift in Reliability

Jane Lim, Cisco                                                       High Speed Serial Links – Design Trends & Challenges

Fabio Urbani, Medtronic                                      Connected Medical Device Design

Joe Dews, AGC Partners                                       Overview of IoT from Investment Banking Perspective

Larry Williams, Ansys                                            Simulation Advances for IoT Devices and Infrastructure

Bill Bottoms, 3MTS                                               Packaging Challenges for IoT

Mark Bachman, UC Irvine                                   Sensors for IoT

EXHIBITION:

Table-top vendor exhibits and sponsors will demonstrate the latest technology enabling IoT designs, supplies and products.

On-line REGISTRATION:
Registration Period: November 1 to December 5

Registration Fee:  IEEE members – $40; Non-members of IEEE – $50; Students – $20; IEEE Student Members – $10

(Prices will increase by $10 for non-student registrations after November 15, 2013)

Register online at http://enablingiot.eventbrite.com

For questions on Registrations, please contact Alex Pfeiffenberger at alexander.pfeiffenberger@broadcom.com.

Date and time:      Friday, December 5^th, 2014 8:30am – 5:00pm (Lunch provided for all attendees)

Location:               Calit2 Building, University of California – Irvine (see map on the next page)

LOCATION & PARKING INSTRUCTIONS

The University parking fee is waived. Parking will be available in the Advanced Parking Structure (APS) off East Peltason Drive.

General Chair

Lawrence Williams, Ansys Corporation, larry.williams@ansys.com

UC Irvine Calit2

Professor G.P. Li, Director, Calit2,gpli@calit2.uci.edu

Technical Program

Wei Koh (Chair), Pacrim Technologies, wkoh2003@hotmail.com

Bob Warren (Co-Chair), Conexant, robert.warren@conexant.com

Sam Karikalan (Keynote), Broadcom Corporation, samkarikalan@ieee.org

Sudhir Sharma (Industry Relation), Ansys Corporation, sudhir.sharma@ansys.com

Registration & Finances:

Alexander Pfeiffenberger, alexander.pfeiffenberger@broadcom.com

Publicity:

Zijie Cai, zijiecai@broadcom.com

Vendor Exhibits & Sponsorships:

Aaron Edwards, Ansys Corporation, aaron.edwards@ansys.com

Local Arrangements:

Lawrence Williams, Ansys Corporation, larry.williams@ansys.com

Chunwei Yu, Broadcom, chyu@broadcom.com

Jiawei Zhang, Broadcom, jiawei@broadcom.com

IEEE Components, Packaging and Manufacturing Technology Society – OC Chapter

The Origins of Silicon Valley: Why and How It Happened

Paul Wesling

IEEE Life Fellow, SF Bay Area Council Communications Director, and SCV CPMT Chapter Advisor

Abstract

Why did Silicon Valley come into being? The story goes back to local Hams (amateur radio operators) trying to break RCA’s tube patents, the sinking of the Titanic, Naval ship communications requirements, Fred Terman and Stanford University, local invention of high-power tubes (gammatron, klystron), WW II and radar, William Shockley’s mother living in Palo Alto, Hetch Hetchy water, and the SF Bay Area infrastructure that developed — these factors pretty much determined that the semiconductor and IC industries would be located in the Santa Clara Valley. And since semiconductor device development and production were centered here, it made sense that Charles (Bud) Eldon of H-P would be asked by his management to start an IRE Group on Product Engineering in Palo Alto, to serve our local engineers (which grew into today’s CPMT Society). Bud went on to become president of the IEEE. Paul Wesling, a CPMT Society Distinguished Lecturer, will give an exciting and colorful history of device technology development and innovation that began in San Francisco and Palo Alto, moved down the Peninsula (seeking lower costs and better housing), and ended up in the Santa Clara Valley during and following World War II. You’ll meet some of the colorful characters — Lee DeForest, Bill Eitel, Charles Litton, Fred Terman, David Packard, Bill Hewlett and others — who came to define the worldwide electronics industries through their inventions and process development. He’ll end by telling us about some current local organizations that keep alive the spirit of the Hams, the Homebrew Computer Club, and the other entrepreneurial groups where geeks gather to invent the future.

Biography

IEEE Components, Packaging and Manufacturing Technology Society – OC Chapter

Glass as a Core Packaging Platform for Next Generation Electronic Devices

Tim Mobley

CEO at Triton Microtechnologies

Abstract

Glass is quickly becoming a dominant material choice driven by the need to have displays and electronics (primarily RF and analog) working within the same platform or form factor. The designer has many hurdles to overcome in order to successfully adopt glass as a core platform for integrating their designs. This presentation will explore glass as a core packaging platform, the motivations that are driving designers to consider glass, the technical challenges that have been solved, and the ones that remain a risk for certain applications. There will be an overall review of the many applications where glass can be used as a core platform.

Biography

IEEE Components, Packaging and Manufacturing Technology Society – OC Chapter

Advance Package Failure Analysis Methods

Winfield Scott

Director, Evans Analytical Group, Inc., Irvine, CA 92618 E-mail: wscott@eag.com

OVERVIEW:

This tutorial will provide an overview of the Failure Analysis process as it relates to electronic packaging. Attendees will learn about:
– The FA methodology and flow
– The importance of a failure’s background history
– Destructive and non-destructive analytical steps including decapsulation and CSAM
– Electrical and physical FA; e.g. curve tracing, cross-section, and SEM
– Advanced techniques: TDR, SQUID and 3D X-ray

WHO SHOULD ATTEND:

IEEE Components, Packaging and Manufacturing Technology Society – OC Chapter

Latest Technologies for high value Capacitors and Inductors integrated with Silicon Interposers

 Franck Murray CEO, IPDIA

Hughes Metras VP Strategic Partnership, CEA-LETI, Visiting Staff at Caltech

Abstract

The integration of passive components in silicon enables various benefits such as form factor improvement, loss reduction but also higher reliability and robustness. To minimize the area required by these passives, IPDiA has developed a Passive Integrated Connecting Substrate offering the capability to integrate 100’s of SMD components in one piece of Silicon. The presentation will detail IPDIA Silicon Integrated Passive Components: high density isolated capacitors, polysilicon resistors, zener diodes and copper inductors. In addition, the capabilities of the research institute Leti to contribute to the development and stabilization of innovative material and process solutions will be illustrated.

Biography

IEEE Components, Packaging and Manufacturing Technology Society – OC Chapter

Micro-Transfer-Printing of Microscale Semiconductor Devices

Chris Bower, Chief Technology Officer

X-Celeprint Ltd

Abstract

Micro-Transfer-Printing (μTP) is an emerging process technology where engineered elastomer print-heads coupled to precision motion controllers are used to “pick-up” arrays of microscale devices from their native growth substrates and then deterministically “transfers” them onto non-native substrates.  Devices compatible with μTP include lasers, LEDs, discrete transistors and silicon integrated circuits.

The first portion of the talk will focus on the science and technology of μTP.  This will include strategies for making “printable” devices and a description of the physical mechanisms utilized during μTP. The second segment of the talk will focus on applications of μTP, including silicon photonics and heterogeneous integration of compound semiconductors with silicon.  

 Biography

IEEE Components, Packaging and Manufacturing Technology Society – OC Chapter

POLYMERS IN ELECTRONIC PACKAGING AFTERNOON TUTORIAL

Jeff Gotro, Ph.D., CMC® – President at InnoCentrix, LLC

Orange County, CA

 OVERVIEW:

The tutorial will provide an overview of polymers and the important structure-property-process-performance relationships for electronic packaging.  The main learning objectives will include:

1. Understand how polymers are used in electronic packaging,
2. Learn why specific chemistries are used depending on the application,
3. Discover how polymers are enabling the next generation packages, and
4. Develop a foundation in rheology and rheological issues in electronic packaging.

MEET THE INSTRUCTOR:

With over 30 years’ experience in polymers for electronic applications and composites, Dr. Jeff Gotro has held scientific and leadership positions at IBM, AlliedSignal, Honeywell, and Ablestik Laboratories. In 2008, Jeff founded InnoCentrix, LLC a boutique technical and management consultancy serving exclusively the polymer industry.  Jeff is an authority in thermosetting polymers and has received invitations to speak at prestigious Gordon Research Conferences (Thermosetting Polymers and Composites). He has presented numerous invited lectures and short courses at technical meetings, has 59 technical publications, 14 issued US patents, and 5 patent applications pending.   Jeff has consulting experience with companies ranging from early-stage start-ups to Fortune 50 companies. His unique combination of deep technical knowledge and business experience allow him to drive client projects to commercial success. Dr. Gotro also provides expert witness services and litigation support in the polymer/plastics field.  He holds a Ph.D. in Materials Science from Northwestern University with a specialty in polymer science, is a Certified Management Consultant (CMC®) from the Institute of Management Consultants (IMC-USA), and is a member of ACS, FEWA, IMAPS, and SAMPE.