Archive for the ‘Event’ Category

Coming Up! April 30 – DRAM Market Forces of Fragmentation and Consolidation

Thursday, April 18th, 2013

IEEE Components, Packaging and Manufacturing Technology Society – OC Chapter

DRAM Market Forces of Fragmentation & Consolidation

Bill Gervasi, Computer Memory Technology Analyst, Discobolus Designs


The market for DRAMs (Dynamic Random-Access Memory) has been a dominant force in computer architecture choices, and a healthy friction always exists between the compromises made for mass adoption and the needs of specific applications.  One mainstream architecture thread – Fast Page through SDRAM through DDR – has dominated the scene but there have been a number of interesting successes and failures to fray from that thread, and many more are on the horizon.  Sometimes it’s amazing what tricks people play to squeeze performance from a technology.  Throughout these transitions and experiments one truism never changes: the tradeoff of volume and price drives success.


Bill Gervasi has been involved in the definition of Double Data Rate SDRAM since its earliest inception.  His background is in computer sciences and career highlights include 19 years at Intel where over the years he was systems hardware designer, software designer, and major accounts manager.  Bill Gervasi joined Intel in 1976 in the computer systems group manufacturing department, eventually leaving Intel in 1995. During that period, the computer industry changed from computers that filled rooms the size of basketball courts to desktop and laptop form factors in nearly every home in the world.

 Since then, Mr. Gervasi specialized in the computer memory technology arena, getting involved in international standards and battles for global dominance for this key part of computer systems. He subsequently was with S3 where he was a graphics architecture specialist and at Transmeta as memory technology analyst.  Most recently he has entered the memory modules world through management positions at Netlist, SimpleTech, and US Modular driving unique memory module configurations. 

Mr. Gervasi is credited with successfully introducing 4 rank and DDR3 registered DIMMs into the JEDEC standardization process. He has served on the JEDEC Board of Directors and chaired committees for DRAM parametrics and small form factor memory modules throughout the development of DDR1, DDR2, and DDR3.  As a chairman of the JEDEC standards organization, he has had a role in paving the memory industry roadmap, and contributed to spreading these standards to the world including engagement with foreign governments. Bill is a public speaker in this niche, generating both excitement and controversy with his aggressive vision for change and progress. Mr. Gervasi holds numerous patents in memory and packaging design, and has performed expert witness testimony in major patent cases.

Bill Gervasi speaks often at technology trade events and offers training for memory technology.  He offers computer memory design, marketing, and analysis services through his company, “Discobolus Designs,” and is the author of Nerd Story a humorous personal history of the computer revolution, available online (ISBN 978-1-4524-4622-6). Find out more at

 April Tech Speaker_Bill Gervasi_2


Date:              Tuesday, April 30, 2013

Location:       Broadcom Corporation, 5300 California Ave., Irvine, CA 92617 – Bldg. 2 Conf. Room 2-1037 

                        Check in at the Security Gate and proceed to Bldg. 2. You will be escorted into the building.

 Time:              5:00-5:30pm: Social time, 5:30-7:00pm: Presentation, 7:00pm: Dinner

 RSVP:            IEEE members and non-members all are welcome to attend.

                     Please RSVP at Please be at the Bldg. 2 entrance by 5:30 pm.

                          For questions regarding RSVP, please contact Cristina Nicoara (

Atomic Layer Deposition/Molecular Layer Deposition for Packaging

Friday, August 3rd, 2012

IEEE CPMT Orange County Chapter will hold August technical meeting as follows:

Topic:     Atomic Layer Deposition/Molecular Layer Deposition for Packaging 

Speaker:    Dr. Y. C. Lee, S.J. Archuleta Professor, Director of DARPA Center for Integrated Micro/Nano-Electromechanical Transducers (iMINT), Administrative Director of Nano Materials Characterization Facility (NCF)

Date:   Thursday, August 16, 2012

Time:   6 – 7pm, dinner (pizza and soda provided by CPMT OC Chapter) will be served at the end of the presentation

Venue: Broadcom Corporation, 5300 California Ave., Irvine, CA 92617 – Bldg. 2 Conf. Room 2-1037 (Salt Creek)

For more details and RSVP, please visit

The Executive Committee of the Chapter invites everyone of you to attend this meeting and actively participate in all our future activities. Also, please feel free to forward this announcement document to all your friends who may be interested in this talk, as this meeting is OPEN to ALL to attend.

You can follow the Chapter activities on our website at or on LinkedIn at


Thanks much for your participation and support.

Best Regards,

Mehdi Saeidi

Co-chair, IEEE CPMT Orange County Chapter Technical Program


(949) 296-5618

Signal Integrity, Power Integrity, and EMI/EMC for Packaging – Aug 23rd

Thursday, August 2nd, 2012

You are invited to the IEEE, CPMT, and Intertek tutorial on:“Fundamentals of Signal Integrity, Power Integrity and EMI/EMC for Microelectronic Packaging and System Design.” Date: August 23, 2012

Location: Lake Forest, CA

8:30 am – 8:50 am Registration and Networking
9:00 am – 5:00 pm (to include a one hour lunch break and one hour lab tour and demo)

This course will teach the fundamentals of IC package electrical performance metrics such as signal integrity, power integrity and electromagnetic compatibility and how to apply those concepts to an advanced IC package design. This often complex content will be delivered at a level that should be accessible to the “lay-engineer”.

Flyer:    IEEE_CPMT_OC_Chapter_Aug_23_2012_Sam_Karikalan_David_OReilly

Topics will Include:

  • The basic principles of interconnect electromagnetics, including RLC parasitics, transmission line behavior, and associated common design challenges such as signal reflections, crosstalk, simultaneous switching noise and power delivery network resonances.
  • The relationship between common signal integrity and power integrity design issues and system level electromagnetic compatibility.
  • Other component level causes for inter-system and intra-system EMC issues.
  • Areas of electrical performance concern in typical wafer level, flip chip and wire bonded packages on laminate / build-up substrates (generic electrical design guidelines will be provided).
  • System-level EMC, with various practical EMI mitigation techniques.

Lab Tour: The event will include a visit to Intertek’s state-of-the-art EMC/EMC compliance test labs for a demonstration of common EMI/EMC phenomena.

Presenter:  Sam Karikalan, Senior Principal Engineer, Broadcom Corporation  AND  David O’Reilly, Engineering TEam Leader, Intertek


Ticket Type                         Cost
IEEE Member                       $250.00
Non IEEE Member                $400.00
Student IEEE Member           $75.00
Student Non IEEE Member    $125.00

For more information, please contact Kimberly Hawkins at or Sam Karikalan at

May Technical Meeting: MEMS in Laminates

Monday, May 7th, 2012

Join us for our May technical meeting!  All are welcomed.

Topic: MEMS in Laminates

Speaker: Prof. Mark Bachman, Dept. of Electrical Engineering and Computer Science, Materials and Manufacturing Technology

University of California, Irvine, CA

Date:  Wednesday, May 16, 2012

Time: 6 – 7pm, dinner (pizza and soda provided by CPMT OC Chapter) will be served at the end of the presentation    

Venue: Broadcom Corporation, 5300 California Ave., Irvine, CA 92617 – Bldg. 2 Conf. Room 2-1037 (Salt Creek) 

For more details and RSVP, please visit

Prof. M. Bachman

RE: January 2012 Presentation

Monday, April 16th, 2012

You can find the slides from Bud Crockett’s informative presentation on palladium copper bonding wire technology here: OC_IEEE PdCu wires Jan_2012


Final Program of 3D IC Workshop now available

Monday, October 31st, 2011

The final program of the CPMT OC Chapter All-Day 3D IC Workshop on Dec 9, 2011 is now available. Please see the final announcement flier for more details. Register at before Nov 25, to avail the early-bird rates. Pls see attach file for details





IEEE CPMT OC Chapter featured in the CPMT Newsletter

Thursday, October 20th, 2011

Memorial Day to Fourth of July – The Birth Story of a New CPMT Chapter – An interview between Eric Perfecto, CPMT Chapter and Membership Director, and Sam Karikalan, CPMT Orange County Chapter Chair has been published on pages 7-9 of the Fall 2011 edition of the CPMT Newsletter


Upcoming Event: Short Course on Thermal Design & Modeling of IC Packages

Monday, October 17th, 2011

Short Course on Thermal Design and Modeling of IC Packages

Date:         Tuesday, November 15th, 2011

Location:   Room 304 (Lunch Room), Henkel Electronic Materials, LLC, 14000 Jamboree Road, Irvine, CA 92606

Time:        12:00-1:00pm: Lunch, 1:00-5:00pm Short Course

Registration Fee: IEEE members – $40; Non-members of IEEE – $50; Students – $25 (includes Sandwich Lunch & Training material) Register online at Number of seats is limited to only 40. For questions on Registrations, please contact Fan Yeung at

For details, see IEEE_CPMT_OC_Chapter_Nov_15_2011_Dr_Sam_Zhao


Upcoming Event: CPMT OC Chapter technical meeting

Tuesday, September 27th, 2011

3D IC/Si Integration Technology  ( by John H. Lau, PhD, IEEE, ITRI Fellow)

Date:           Wednesday, October 12th, 2011

Location:    Broadcom Corporation, 5300 California Ave., Irvine, CA 92617 Bldg. 2 Conf. Room 2-1037 (Salt Creek)

Time:         5:30-6:00pm: Social time, 6:00-7:00pm: Presentation, 7:00pm: Dinner (Pizza and Soda provided by CPMT OC Chapter)

RSVP:         IEEE members and non-members all are welcome to attend.

For detailed information, please see attached flyer  IEEE_CPMT_OC_Chapter_Oct_12_2011_John_Lau

IEEE CPMT OC Chapter All-Day Workshop on 3D Integrated Circuits

Tuesday, September 6th, 2011

The IEEE Components, Packaging and Manufacturing Technology (CPMT) Society – Orange County Chapter is pleased to announce its first annual All-Day Workshop.

Following are the details:

Topic: 3D Integrated Circuits – Technologies enabling the Revolution

Date: Friday, Dec 09, 2011 Time: 9:00am – 4:00pm

Venue: Jazz Semiconductor Auditorium, 4321 Jamboree Road, Newport Beach, CA 92660

This workshop will feature industry experts on enabling technology fields such as Architecture, Materials, Manufacturing Processes, Equipment, Test and Design tools that are bringing 3D Integrated Circuits to the mainstream. Please see the attached Advance Announcement flyer for more details.