Last 2013 Tech Meeting – Sept. 12! IC ESD/Latch-up Mechanisms and Testing

IEEE Components, Packaging and Manufacturing Technology Society – OC Chapter

Integrated Circuit ESD/Latch-up Mechanisms and Testing

Barry Fernelius, Manager at Evans Analytical Group (EAG)

 Orange County, CA



Design engineers are increasingly being challenged to reduce the incidence of latch-up. At the same time, this task is made more difficult as devices become more complex and process technologies continue to shrink. The JEDEC latch-up spec is also constantly evolving. In this presentation, attendees will learn:

  • An overview of latch-up test and spec
  • Test guidelines, techniques, and best practices
  • Why latch-up is challenging
  • What’s coming in JESD78E


Mr. Barry Fernelius is the manager of the ESD and latch-up labs at Evans Analytical Group. He has been working in the semiconductor industry since 1981, and he’s been involved with the JEDEC ESD and latch-up specs for more than twenty years. He’s also been a fab engineer for Hewlett-Packard and a senior reliability engineer for Agilent and Avago.

Barry Fernelius

 Date: Thursday, September 12, 2013

Location: Broadcom Corporation, 5300 California Ave., Irvine, CA 92617 – Bldg. 2 Conf. Room 2-1034

Check in at the Security Gate and proceed to Bldg. 2. You will be escorted into the building.

Time: 5:30-6:00pm: Social time, 6:00-7:00pm: Presentation, 7:00pm: Dinner (free for attendees!)

RSVP: IEEE members and non-members all are welcome to attend.

Please RSVP at Please be at the Bldg. 2 entrance by 6:00 pm.

For questions regarding RSVP, please contact Cristina Nicoara (