2022-2023 Officers  –  IEEE EDS Washington DC/Northern Virginia Chapter

Xiangyi “Tony” Guo, Chair

Dr. Tony Guo has worked in semiconductor R&D and manufacturing for over 20 years. From 1997 to 2001, he began his semiconductor career at Philips as an application engineer for circuit design & firmware optimization. From 2002 to 2005, he was a research assistant at Microelectronics Research Center in the University of Texas at Austin, and graduated with PhD degree in EE. He had developed wide bandgap SiC APD for single photon counting with record low dark current. From 2006 to 2017, he joined Micron Technology Virginia, and had held different process integration engineering positions for memory devices. He has experience on electron device characterization and modeling, yield prediction and improvement, device qualification and reliability improvement, data mining, big data analytics, and project management. Dr. Guo had published many IEEE journal papers, Micron TLP (Technical Leadership Program) and conference papers. His 1st-author paper on PMOS NBTI improvement had been awarded as the best TLP paper in 2014. As a senior member of IEEE, he had actively involved in several EDS events such as IEEE Memory Day, and volunteered STEM events. He is an IEEE VoLT program (2017) graduate. Currently he is a senior principal device engineer at Northrop Grumman. 

Joseph J. Kopanski, Vice Chair

Joseph J. Kopanski received the B.S. degree in Applied Physics and the M.S. degree in Electrical Engineering and Applied Physics from Case Western Reserve University in 1982 and 1985, respectively. His thesis involved the development of semiconductor processing technology for silicon carbide MOSFETs and blue light emitting diodes. He joined the National Institute of Standards and Technology (then the National Bureau of Standards) in Gaithersburg, MD in 1985 where he is currently a member of the technical staff. His research interests are currently focused on using scanning probe techniques, such as scanning capacitance microscopy, tunneling atomic force microscopy, and scanning Kelvin force microscopy for electrical transport characterization of nanostructures and back end of the line characterization issues. He became Group Leader of the Advanced Device Reliability and Characterization Group, Engineering Physics Division of the NIST Physical Measurement Laboratory in 2015. Mr. Kopanski is also the director of the Electrical Engineering Summer Undergraduate Research Fellowship (SURF) program in the Physical Measurement Laboratory of NIST.

Murty Polavarapu, Treasurer

Murty Polavarapu advises companies on defense microelectronics, with emphasis on radiation hardening and nanotechnology applications. Immediately prior he spent three decades making significant contributions to advanced semiconductor logic and memory devices for companies including BAE Systems, IBM, Lockheed Martin, Micron, and Toshiba. He holds eleven patents and received numerous awards including the BAE Systems Chairman’s Silver Award, Dominion Semiconductor President’s Award and IBM Outstanding Technical Achievement Award. He is a Fellow of Washington Academy of Sciences.

Mr. Polavarapu earned his Masters in Electrical Engineering from Howard University and his Masters in Technology Management from University of Pennsylvania. He is motivated to help young people learn and has a keen interest in developing future engineers through STEM activities; he served as a United States Peace Corps volunteer physics teacher in Fiji and co-founded a non-profit organization to help bring computers to schools in Ethiopia. Murty is an avid world traveler.

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