IEEE Nanotechnology Council
Advancing Nanotech for Humanity

EiC’s Picks from IEEE Transactions on Nanotechnology

TNANOBANNEREiC’s Picks from IEEE Transactions on Nanotechnology

Papers selected by the Editor-in-Chief and featured here are examples of papers published in TNANO having high academic impacts, practical applications, or engineering appeal.

Design Guidelines for Sub-12 nm Nanowire MOSFETs.
Salmani-Jelodar, M. ; Mehrotra, S.R. ; Ilatikhameneh, H. ; Klimeck, G.

IEEE Transactions on Nanotechnology Vol. 14 ,  Issue 2, pp. 210 – 213, (January 26, 2015) DOI:10.1109/TNANO.2015.2395441

Traditional thinking assumes that a light effective mass (m*), high mobility material will result in better transistor characteristics. However, sub-12-nm metal-oxide-semiconductor field effect transistors (MOSFETs) with light m* may underperform compared to standard Si, as a result of source to drain (S/D) tunneling. An optimum heavier mass can decrease tunneling leakage current, and at the same time, improve gate to channel capacitance because of an increased quantum capacitance (Cq). A single band effective mass model has been used to provide the performance trends independent of material, orientation and strain. This paper provides guidelines for achieving optimum m* for sub-12-nm nanowire down to channel length of 3 nm. Optimum m* are found to range between 0.2-1.0 m0 and more interestingly, these masses can be engineered within Si for both p-type and n-type MOSFETs. m* is no longer a material constant, but a geometry and strain dependent property of the channel material.

3-D Finite Element Monte Carlo Simulations of Scaled Si SOI FinFET With Different Cross Sections.

Nagy, D.; Elmessary, M.A. ; Aldegunde, M. ; Valin, R. ; Martinez, A. ; Lindberg, J. ; Dettmer, W.G. ; Peric, D. ;Garcia-Loureiro, A.J. ; Kalna, K.

IEEE Transactions on  Nanotechnology Vol. 14 , Issue 1, pp. 93-100 (November 5, 2014) DOI:10.1109/TNANO.2014.2367095

Nanoscaled Si SOI FinFETs with gate lengths of 12.8 and 10.7 nm are simulated using 3-D finite element Monte Carlo (MC) simulations with 2-D Schrodinger-based quantum corrections. These nonplanar transistors are studied for two cross sections: rectangular-like and triangular-like, and for two channel orientations: (100) and (110). The 10.7-nm gate length rectangular-like FinFET is also simulated using the 3-D nonequilibrium Green’s functions (NEGF) technique and the results are compared with MC simulations. The 12.8 and 10.7 nm gate length rectangular-like FinFETs give larger drive currents per perimeter by about 33- 37% than the triangular-like shaped but are outperformed by the triangular-like ones when normalised by channel area. The devices with a (100) channel orientation deliver a larger drive current by about 11% more than their counterparts with a (110) channel when scaled to 12.8 nm and to 10.7 nm gate lengths. ID – VG characteristics obtained from the 3-D NEGF simulations show a remarkable agreement with the MC results at low drain bias. At a high drain bias, the NEGF overestimates the on-current from about VG – VT = 0.3 V because the NEGF simulations do not include the scattering with interface roughness and ionized impurities.

Controlling Grain Size and Continuous Layer Growth in Two-Dimensional MoS2 Films for Nanoelectronic Device Application.

Jaeho Jeon; Sung Kyu Jang ; Su Min Jeon ; Gwangwe Yoo ; Jin-Hong Park ; Sungjoo Lee.
IEEE Transactions on Nanotechnology Vol. 14 , Issue 2, pp. 238-242 (December 22, 2014) DOI:10.1109/TNANO.2014.2381667
We report that control over the grain size and lateral growth of monolayer MoS2 film, yielding a uniform large-area monolayer MoS2 film, can be achieved by submitting the SiO2 surfaces of the substrates to oxygen plasma treatment and modulating substrate temperature in chemical vapor deposition (CVD) process. Scanning electron microscopy and atomic force microscopy images and Raman spectra revealed that the MoS2 lateral growth could be controlled by the surface treatment conditions and process temperatures. Moreover, the obtained monolayer MoS2 films showed excellent scalable uniformity covering a centimeter-scale SiO2 /Si substrates, which was confirmed with Raman and photoluminescence mapping studies. Transmission electron microscopy measurements revealed that the MoS2 film of the monolayer was largely single crystalline in nature. Back-gate field effect transistors based on a CVD-grown uniform monolayer MoS2 film showed a good current on/off ratio of ~106 and a field effect mobility of 7.23 cm2/V·s. Our new approach to growing MoS2 films is anticipated to advance studies of MoS2 or other transition metal dichalcogenide material growth mechanisms and to facilitate the mass production of uniform high-quality MoS2 films for the commercialization of a variety of applications.

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