Rashmi Jha

Dr. Rashmi Jha

Associate Professor at the University of Cincinnati
Talk Track: Emerging Electronics and Microsystems
Talk Title: Gate Controlled 3-Terminal Resistive Random Access Memory Devices for Reconfigurable, Neuromorphic, and Trusted Microelectronics



Dr. Rashmi Jha is currently an Associate Professor in Electrical Engineering and Computing Science Department at the University of Cincinnati. She worked as a Process Integration Engineer for Advanced CMOS technologies at IBM Microelectronics prior to moving to academia. She finished her Ph.D. and M.S. in Electrical Engineering from North Carolina State University in 2006 and 2003, respectively, and B.Tech. in Electrical Engineering from IIT Kharagpur, India in 2000. She has more than 14 years of experience in the areas of Nanoelectronic Logic and Memory Devices. She has been granted 12 US patents and has authored/co-authored several publications in the areas of nanoelectronic devices. She has been a recipient of Summer Faculty Fellowship Award from US Air force Research Laboratory in 2017, CAREER Award from the National Science Foundation (NSF) in 2013, IBM Faculty Award in 2012, IBM Invention Achievement Award in 2007, Materials Research Society’s Graduate Student Award in 2006, Applied Materials Fellowship Award in 2005-2006, and the best student paper award nomination in IEEE International Electron Devices Meeting (IEDM) in 2005. She is the director of Microelectronics and Integrated-systems with Neuro-centric Devices (MIND) laboratory at the University of Cincinnati. Her current research interests lie in the areas of Neuromimetic Devices, Bio-inspired Circuits and Systems, Neuromorphic Computing Systems, Resistive Random Access Memory Devices, Spintronics, Cyber-Security, Wearable Computing and IoT, and Energy Harvesting Devices.


2-Terminal Resistive Random Access Memory (ReRAM) devices have been widely studied for high-density data storage, neuromorphic, and hardware security applications. While 2-terminal ReRAM devices are attractive from scalability perspective, they suffer from the issues of variability in states, limited endurance, and necessity of access devices to overcome sneak currents in crossbar arrays. Additionally, availability of just 2-terminals imposes challenges for simultaneous read and write in applications where dynamic reconfiguration is required. To address some of these issues, our research efforts in the ares of developing gate-controlled 3-terminal ReRAM devices will be discussed in this talk. Performance of experimental devices will be presented and opportunities to integrate these devices for general purpose reconfigurable, neuromorphic, and trusted microelectronics will be discussed.