Dr. Minh Nguyen
Track: Photonics Devices and Systems
Talk Title: Direct integration of III-V MWIR detectors with Si-based integrated circuits: Material growth and device schemes
Minh Nguyen is a Senior Research Engineer in the Sensors and Electronics Laboratory at HRL Laboratories. Prior to joining HRL in 2014, he received his PhD in Electrical Engineering from Northwestern University and helped positions in diverse research environment such as Research Assistant Professor at Northwestern University, technical director of a small business, director’s postdoctoral fellow at Los Alamos National Lab. He has over 10 years of focused experience in developing superlattice–based infrared detectors and imagers, encompassing the areas of device modeling/design, epitaxial growth, device fabrication and testing. At HRL laboratories, Nguyen has been PM/PI for a number of research projects using III-V superlattice material systems for infrared detection and topological quantum computation. He has authored/co-authored six book chapters, more than 80 technical papers with over 2700 citations and an h-index of 32.
High performance infrared focal plane arrays play a critical role in a wide range of imaging applications. However the high cost associated with the required serially processed die-level hybridization is major barrier that has thwarted III-V MWIR detector technology from penetrating large-volume, low-cost markets. Under the DARPA Wafer Scale Infrared Detectors (WIRED) program, we will demonstrate wafer scale, direct growth of MWIR InAsSb material on ROICs as a means to achieve significant cost reduction of MWIR imagers. We utilize a metalorganic chemical vapor deposition (MOCVD) based Lateral Epitaxial Overgrowth (LEO) technique to grow predominantly oriented, single-crystal-like InAs films that nucleate at small openings on ROIC-like templates where the underlying Si (001) surface is exposed to seed the crystal orientation of the InAs epilayer. Lateral growth of the InAs islands following nucleation in narrow trenches is demonstrated with high crystallinity (as assessed by transmission electron microscopy), together with the suppression of unwanted deposition on the dielectric mask used to pattern the Si substrate. The MOCVD-LEO process is performed a low growth temperature (<450oC), which is within the allowable thermal budget of the underlying CMOS ROIC. Additionally, novel detector structures are implemented to contend with the parasitic leakage paths encountered in materials that consist of disordered polycrystalline regions and grain boundaries. In this talk, we will present WIRED Phase I’s progress and results, comprising of the evolution of our low temperature MOCVD-LEO scheme and the performance of barrier-based detector structures implemented in InAs-based disordered materials.