Date/Time: 2015 January 23 (Fri) 15:00-16:00
Location: Tokyo Institute of Technology, Lecture Room 906 @ 9F, South Bldg.3, Ookayama Cumpus
http://www.titech.ac.jp/english/maps/ookayama/ookayama.html
#35. South Bldg. 3
Meeting Agenda:
(1) Lecture 1: 15:00-16:00
Title: CAD and Circuit Techniques for Power Optimization in FPGA Interconnect
Speaker: Prof. Jason Anderson (University of Toronto, Canada)
sponsored by
IEEE CEDA All Japan Joint Chapter
No Admission Charge.
The following seminar will be also held in the same place.
(2) Lecture 2: 16:00-17:00
Title: Trends on Micro and Nano electronics
Speaker: Prof. Ricardo Reis (Universidade Federal do Rio Grande do Sul)
sponsored by
IEEE CASS Japan Chapter
No Admission Charge.
