IEEE Distinguished Lecture – Evolution of Si CMOS Technologies to Sub-10 nm Generation

“Evolution of Si CMOS Technologies to Sub-10 nm Generation” by Professor Hiroshi Iwai, Tokyo Institute of Technology, Japan. IEEE Distinguished Lecturer.

Date:  November 30, 2012 (Friday)
Time:  2:30 pm – 3:15 pm
Venue:  PSDC, 1 Jalan Sultan Azlan Shah, 11900 Bayan Lepas, Penang, Malaysia

Abstract

Recently, CMOS downsizing has been accelerated very aggressively in both production and research, and even beautiful transistor operation of several nm gate length CMOS devices were reported in conferences. However, many serious problems are expected for implementing small-geometry MOSFETs into large scale integrated circuits. It is still questionable if we can successfully introduce deep sub-10 nm CMOS LSIs into market, because the problems expected at this moment – such as Ion/Ioff ratio, current drive, variation in the electrical characteristics, concerns for the yield, reliability and manufacturing cost. Considering the above situation, we have conducted nano-CMOS studies in advance to provide possible solutions to the future expected problems. The conclusion obtained by the study was that, in the nano-CMOS era, aggressive introduction of new materials, processes, structures, and operation concepts is required to solve the problems. Especially, the thinning of the gate oxide is the bottleneck of the future down-scaling, and thus, new materials and process technologies which enable decrease in the EOT (Equivalent Oxide Thickness) value less than 0.5 nm are very important. Also, changing the material of source/drain from semiconductor to metal is necessary to suppression of the diffusion of the dopant and thus, to secure the effective channel length less than several nm. Multigate structure such as Fin, Tri-gate, or nanowire is inevitable to suppress the short-channel effect.

Unfortunately, there are no candidates among the so-called ‘beyond CMOS’ new devices, which are believed to really replace CMOS transistors of highly integrated circuits in near future. Thus, our opinion is that we need to still continue to develop CMOS based transistors with ‘More Moore’ approach with combining that of ‘More than Moore’. Good news is that Si Nanowire FETs have been found to have very promising characteristics with high Ion/Ioff ratio and high drive current. Also, La-silicate high-k gate insulator and Ni-silicide source/drain have been proven to be very promising candidates. In this talk, future of nano-CMOS technologies which enable downsizing for next several generations are presented.

Speaker

Hiroshi Iwai received the B.E. and Ph.D. degrees in electrical engineering from the University of Tokyo and worked in the research and development of integrated circuit technology for more than 25 years in Toshiba. He is now a professor of Frontier Research Center and Dept. of Electronics and Applied Physics, Interdisciplinary Graduate School of Science and Engineering, Tokyo Institute of Technology, Yokohama, Japan. Since joining Toshiba, he has developed several generations of high density static RAM’s, dynamic RAM’s and logic LSI’s including CMOS, bipolar, and Bi-CMOS devices. He has also been engaged in research on device physics, process technologies, and T-CAD related to small-geometry MOSFETs and high speed bipolar transistors. He has authored and coauthored more than 700 international and 350 domestic journal/conference papers.

He has served on many committees of conferences and editors of journals, as well as a member of many evaluation committee of public organizations. For example, a member of IEEE Board of Directors, and IEEE Division 1 Director for 2010-11, the President of the IEEE Electron Devices Society, an elected member of the IEEE EDS AdCom, an editor of IEEE EDS Newsletter, a guest editor of IEEE Trans. on Electron Devices, and an editor of the Proceedings of many ECS Symposia. He has served as a visiting professor for Japanese, Chinese and Indian universities for many years.

His awards include Local Commendation for Invention from Japan Institute of Invention and Innovation (1990, 2005), Grand Prize of Nikkei BP Technology Awards (1994), IEEE EDS Paul Rappaport Award (1994), IEICE ES Electronics Award (1998), IEEE EDS J.J.Ebers Award (2001), and JSAP Award for the best paper (2002), IEEE BCTM Award (2007), Yamazaki-Teiichi Prize (2007), IEEE 2008 EDS Distinguished Service Award (2008), The Commendation for Science and Technology by the Minister of Education, Culture, Science and Technology, Prizes for Science and Technology, Development Category Award (2009).

His current research interests are Nano CMOS, Power MOSFET and Emerging Technologies: Si Nanowire MOSFETs, III-V MOSFETs, GaN Power MOSFETs, Diamond FETs, High-k gate insulator technology, Metal/silicide S/D technology.

Dr Iwai is, a fellow of IEEE, a fellow of Institute of Electrical Engineers Japan, a fellow of the Japan Society Applied Physics, and a fellow of the Institute of Electronics, Information and Communication Engineers of Japan.