“Design Techniques and CMOS Implementation of Low Noise Amplifier (LNA)” by Professor S.S. Jamuar, School of Microelectonics Engineering, University Malaysia Perlis.

March 19, 2015 (Thursday)
7:00 pm – 8:30 pm
PSDC, Room 1202, 1 Jalan Sultan Azlan Shah, 11900 Bayan Lepas, Penang, Malaysia

Admission is free.  Refreshments will be served at 6:30 pm.  Network and interact with like-minded engineers and researchers before the seminar begins.

Abstract

The rapid growth of portable RF communication systems in various standards has led to the demand for one chip to cover several standards such as WCDMA, WLAN, GSM etc.  The RF front-end would have to cover a huge range of different carrier frequencies for all standards, thus to integrate all this in one chip would be very area inefficient. Competitive technologies have emerged for wireless system implementation taking into account scaling, integration ability and cost.

Any wireless system consists of a transmitter and a receiver. The transmitter delivers the signal modulated through an antenna while the receiver recovers the received signal from the antenna. The performance of the system depends on the system design, circuit design and system requirement. The acceptable level of noise varies with system requirements. Noise and interference as unwanted signals set a limit on the usable signal level at the output. Thus, for the signal to be usable, the signal power must be larger than the noise power specified by minimum signal-to- noise ratio.

The stringent requirements for different wireless systems place particular emphasis on each building blocks of the receiver. Thus, improved design techniques are needed for different standard of RF systems. A receiver system consists of the following circuits: a low noise amplifier, mixer, voltage-controlled oscillator (VCO), intermediate frequency (IF) amplifier and filters. Low noise amplifier (LNA) is typically the first active stage for the RF front-end. Its main function is to amplify low signal without adding noise, thus preserving the signal-to-noise ratio (SNR) of the system at low power consumption. Many tradeoffs involved in designing the LNA such as noise figure (NF), linearity, gain, impedance matching and power dissipation. Therefore, proper LNA design considerations and techniques are crucial in today’s communication technology.

A novel LNA is typically implemented using voltage-mode techniques. Rivaling classical designs, techniques for a variable-gain LNA can be designed using current mode approach. The tutorial includes current-mode approach, which offers several advantages that might be suited for certain communication standard. The tutorial would covers steps involved in designing a LNA – DC biasing voltage, stability design analysis, noise matching and impedance matching.

This tutorial would place an emphasis on improved design techniques for one of the building block of RF system, low noise amplifier (LNA). In order to meet the objectives of tutorial, DC biasing techniques, impedance matching techniques, noise matching and stability analysis will be discussed. Voltage mode design and current mode design techniques will be elaborated. Variable gain low noise amplifier design techniques will also be discussed. All the design techniques and simulations presented in the tutorial will be based on EDA tools.

Speaker

S.S. Jamuar received his M. Tech and Ph. D. in Electrical Engineering from Indian Institute of Technology, Kanpur, India in 1970 and 1977 respectively. He worked as Research Assistant, Senior Research Fellow and Senior Research Assistant from 1969 to 1975 at IIT Kanpur. During 1975-76, he was with Hindustan Aeronautics Ltd., Lucknow. Subsequently he joined the Lasers and Spectroscopy Group in the Physics Department at IIT Kanpur, where he was involved in the design of various types of Laser Systems. He joined as Lecturer Electrical Engineering Department at Indian Institute of Technology Delhi in 1977, where he became Assistant Professor in 1980. He was attached to Bath College of Further Education, Bath (UK), Aalborg University, Aalborg (Denmark) during 1987 and 2000. He was a Professor in the Department of Electrical Engineering at IIT Delhi from 1991 to 2003. He was Consultant to UNESCO during 1996 in Lagos State University, Lagos (Nigeria). He was with University Putra Malaysia during 1996 – 97 and 2001 – 2009 in the Faculty of Engineering and Faculty of Engineering, University of Malaya (Malaysia) 2009-2013. Presently he is Professor in the School of Microelectronics Engineering at University Malaysia Perlis since November 2013. He has been teaching and conducting research in the areas of Electronic Circuit Design, Instrumentation and Communication Systems. He has about 65 papers in the International Journals and has attended several International Conferences and presented papers. He recently received Taiwan Patent on “A Simulation Circuit Layout Design for Low Voltage, Low Power and High Performance Type II Current Conveyor”. He is recipient of Meghnad Saha Memorial Award 1976 from IETE, Distinguished Alumni Award from BIT Sindri in 1999, Best paper award in IETE journal of Education 2004 from IETE. He is senior member of IEEE and Fellow of Institution of Electronics and Telecommunications Engineering (India). He is on the Editorial Board of Wireless Personnel Communication Journal. He was the Chapter Chair for IEEE CAS Chapter in Malaysia.