“Compact Modeling of Nano-Transistors from a Circuit Simulation Perspective” by Mansun Chan, PhD, Department of EEE, HKUST, Clear Water Bay, Kowloon, Hong Kong, China.

Date:  August 24, 2010 (Tuesday)
Time:  7:30pm – 9:00pm; 6:30pm networking
Venue:  PSDC, Room 2302, 1 Jalan Sultan Azlan Shah, 11900 Bayan Lepas, Penang

Admission is free

Refreshments will be served before the lecture.  Network and interact with like-minded engineers and researchers before the seminar begins.

Abstract

With the recent advance of CMOS technology to the 32nm range, there is a major concern to continue the scaling roadmap.  Many new devices have been proposed, but selecting the right structure is not a simple task.  A lot of activities have been devoted to develop compact models for the unconventional nano-transistors, in particular, Multigate CMOS.  While the different groups have spent a lot of effort to develop compact model for Multigate CMOS devices, no much attentions have been devoted to the interface to circuit simulators.

In this presentation, the issues of developing a circuit simulator friendly compact model for nano-Transistors will be described.  A number of approaches to describe the physical behavior of Multigate MOSFETs, including direct charge calculation, surface potential derivation and carrier formulation will be described.  It will be followed by a discussion on how the accelerated technology development may impact the traditional modeling methodologies. A new paradigm to incorporate modern software engineering methodology to shorten model development cycle will be presented.

Speaker

Dr Mansun Chan received his BS degree in Electrical Engineering (highest honors) and BS degree in Computer Sciences (highest honors) in 1990 and 1991 respectively, both from University of California at San Diego. He completed his MS degree in 1994 and Ph.D degree in 1995 at University of California at Berkeley. During his undergraduate study, he has been working with Rockwell International Laboratory on Heterojunction Bipolar Transistor (HBT) modeling, where he developed the self-heating SPICE model for HBT. His research at Berkeley covered a broad area in silicon devices ranging from process development to device design, characterization, and modeling. A major part of his work was on the development of record breaking Silicon-On-Insulator (SOI) technologies. Dr. Chan has also maintained a strong interest in device modeling and circuit simulation. He is one of the major contributors to the unified BSIM model for SPICE, which has been accepted by most US companies and the Compact Model Council (CMC) as the first industrial standard MOSFET model. In January 1996, he has joined the EEE faculty at Hong Kong University of Science and Technology. His research interests include nano-device technologies, image sensors, SOI technologies, high performance IC, 3D Circuit Technology, device modeling and Nano BIOMEMS technology. Between July 2001 and December 2002, he was a Visiting Professor at University of California at Berkeley and the Co-director of the BSIM program. He is currently still consulting on the development of the next generation BSIM model.

Dr Chan is a recipient of the UC Regents Fellowship, Golden Keys Scholarship for Academic Excellence, SRC Inventor Recognition Award, Rockwell Research Fellowship, R&D 100 award (for the BSIM3v3 project), Teaching Excellence Appreciation award (1999) and other awards. He is a Senior Member and Distinguished Lecturer of IEEE.