“CMOS Device Technology and Scaling Challenges in FPGAs” by Jeff Watt, PhD, Technology Architect, Altera Corporation, USA.

Date:  May 6, 2010 (Thursday)
Time:  7:30pm – 8:30pm; 6:30pm networking
Venue:  PSDC, Room 2301, 1 Jalan Sultan Azlan Shah, 11900 Bayan Lepas, Penang

Admission is free

Refreshments will be served before the lecture.  Network and interact with like-minded engineers and researchers before the seminar begins.

Abstract

CMOS device scaling has enabled dramatic growth in the performance, capacity and capability of field programmable gate arrays (FPGAs). Altera’s 40nm Stratix IV FPGA represents one of the most advanced CMOS logic devices in production today with up to 820k logic elements, 22.4Mb of embedded SRAM, 1360 18×18 multipliers and 48 high-speed transceivers running at up to 11.3Gbps.  While every process generation brings new challenges, the difficulty of meeting design goals has been increasing significantly since the 90nm technology node.  Transistor dimensional scaling has led to increases in variability due to random dopant fluctuations.  The use of aggressive process-induced strain and sub-wavelength lithography has caused dramatic increases in layout context variability.  The desire to continually increase speed and density has created challenges in the control of active power and off-state leakage currents.  The supply voltage scaling to meet active power and reliability requirements has led to limited voltage headroom in analog circuits and other fundamental FPGA building blocks.

In this talk, we will review these challenges created by device scaling and the solutions that have been implemented in the process technology and design methodology to enable a successful 40nm product.  We will also describe future challenges which are expected as we scale device technology beyond 40nm and some of the potential solutions which will allow continued increases in performance, capacity and capability.

Speaker

Jeff Watt is Technology Architect at Altera Corporation, where he oversees compact model development and new technology initiatives.  Prior to joining Altera, Jeff was at Cypress Semiconductor where he served as device engineering manager and led the development of transistor processes from 0.65um to 90nm technology nodes.  He was also responsible for SPICE model development and ESD reliability.

Jeff received his BS in Electrical Engineering from Queen’s University, Kingston, Canada in 1983 and his Ph.D. in Electrical Engineering from Stanford University in 1989.  He has over 30 US patents in the areas of CMOS processing, device structures, circuits and ESD protection.  He is a Senior Member of the IEEE, has served on the technical committee of the VLSI Technology Symposium and is past chairman of the Santa Clara Valley Chapter of the Electron Devices Society.